1. Field of the Invention
The present invention relates to computing systems, and more particularly, to synchronizing serial bit stream data for PCI Express devices.
2. Background of the Invention
Computing systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and streaming storage devices (for example, tape drives). In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system.
Host systems often communicate with peripheral devices via an interface such as the Peripheral Component Interconnect (“PCI”) interface, a local bus standard using parallel data transfer that was developed by Intel Corporation®, or the extension of PCI known as PCI-X. More recently, PCI Express, a standard interface incorporating PCI transaction protocols at the logical level, but using serial data transfer at the physical level has been developed to offer better performance than PCI or PCI-X.
Host systems are used in various network applications, including TCP/IP networks, storage area networks (“SANs”), and various types of external device attachment. In SANs, plural storage devices are made available to various host computing systems. Data is typically moved between plural host systems and storage systems (or storage devices, used interchangeably throughout this specification). The connectivity between a host system and networks or external devices is provided by host bus adapters (“HBAs”), which plug into the host system. HBAs may attach to the host system via a standard interface such as PCI Express.
PCI Express HBAs receive serial data streams (bit streams), align the serial data and then convert it into parallel data for processing. PCI Express HBAs operate as transmitting devices as well as receiving devices using the Comma sequence for identifying symbol boundaries.
PCI Express is an Input/Output (“I/O”) bus standard (incorporated herein by reference in its entirety) that is compatible with existing PCI cards. PCI Express uses discrete logical layers to process inbound and outbound information. In the PCI Express terminology, a serial connection between two devices is referred to as a link.
Various other standard interfaces are also used to move data between host systems and peripheral devices. Fibre Channel is one such standard. Fibre Channel (incorporated herein by reference in its entirety) is an American National Standard Institute (ANSI) set of standards, which provides a serial transmission protocol for storage and network protocols.
PCI Express, Fibre Channel and other serial interfaces use 8-bit to 10-bit encoding, in which each 8-bit character of source data is encoded into a 10-bit symbol prior to transmission. A receiving device decodes the 10-bit data to recover the original 8-bit character. 8b-10b encoding provides a number of advantages such as the ability to embed clocking information into a serial bit stream and the ability to detect transmission errors.
In order to recover data from a serial bit stream, the receiving PCI Express device performs clock recovery, de-serialization and symbol lock. In clock recovery, the receiving device generates a serial bit clock that is phase locked to the incoming serial bit stream. This is also known as bit synchronization. For de-serialization, the recovered clock is used to sample the incoming serial bit stream and converts it into parallel data.
For symbol lock, the boundary between consecutive 10-bit symbols is determined and the de-serialized data is aligned to the boundary. After the symbol lock, the 10-bit data is sent to an elastic buffer and then the 10-bit data is decoded to 8-bit data for further processing.
A COMMA symbol is a special bit pattern that is often used to determine symbol and word alignment in a serial stream of data. K28.5 Comma symbol is a unique bit pattern used in bit streams to identify special control sequences not normally found in conventional user data. The 10-bit encoding of the Comma symbol is unique because it is the only symbol that contains two bits of one polarity followed by five bits of opposite polarity, i.e., 0011111010b or 1100000101b. The nature of the 8-bit to 10-bit coding provides a comma sequence that does not occur in a non-comma character, nor in any consecutive combination of non-comma characters, and hence, identifies symbol boundaries.
Once a Comma symbol (or sequence) is detected, the receiving device assumes that the received symbols that follow will be on the same 10-bit boundary. The receiving device also assumes that data is aligned after the Comma character is detected. However, in reality, a data stream may get misaligned due to single bit errors and cause various processing errors. Errors may include loss of bit synchronization and random bit errors. The former may cause bits to be added to or deleted from the de-serialized data, resulting in loss of symbol lock; the latter causes incorrect values to be assigned to one or more bits without loss of synchronization or loss of symbol lock.
Most serial protocol standards specify exact requirements for detecting symbol lock and for detecting loss of symbol lock. Such is not the case with the PCI Express standard, which has left the functional requirements for symbol lock to designers of PCI-Express devices.
Conventional symbol lock techniques used for interfaces such as Fibre Channel do not provide an effective solution for PCI Express applications, as described below. In Fibre Channel, symbol alignment involves aligning to transmission word boundaries, where a word is four consecutive 10-bit symbols. If a transmission word contains a comma character, then the comma character is expected to be in the first symbol only.
In Fibre Channel, comma characters occur frequently; there is a minimum of 6 ordered sets transmitted in an inter-frame gap following every frame of 2112 symbols or less, where an ordered set is a transmission word containing a comma character followed by a prescribed sequence of non-comma characters. The Fibre Channel symbol lock requirement calls for detection of 3 ordered sets, each starting with a comma, with no intervening invalid transmission words. Once symbol lock is achieved, the symbol lock circuit monitors the data stream for the occurrence of transmission errors. If a sequence of 7 consecutive transmission words contains 4 or more invalid transmission words, then a loss of symbol lock is declared, and the initial alignment procedure is repeated.
Although it uses the same 8b-10b coding set, PCI Express differs from Fibre Channel, which makes the above method impractical. First, PCI Express does not group symbols into transmission words, so an ordered set may begin on any symbol that is not part of a packet. Thus, a symbol lock circuit for PCI Express needs to examine individual symbols rather than transmission words. Second, PCI Express devices do not transmit comma characters as frequently, except during training sequences, which are used to establish bit synchronization and symbol alignment during link initialization and following low-power link states during which data transmission is suspended. During normal full-power operation, there may be as many as 5650 symbols between comma characters. This corresponds to the maximum allowed scheduling interval for skip ordered sets, which are ordered sets per the PCI Express standard for prevention of overflow or underflow of the elastic buffers of receiving devices, plus the maximum residual packet length before the scheduled skip ordered set is actually transmitted. Furthermore, because skip ordered sets are isolated, (unlike in Fibre Channel, in which ordered sets are clustered in the inter-frame gaps), the receipt of 3 commas for symbol lock acquisition would span multiple PCI Express packets.
Bit error rates are typically expected to be low, but are not bounded by the PCI Express standard, so the symbol lock circuit is expected to perform well in noisy systems with high bit error rates. In such an environment, there exists a significant probability that an alignment attempt using the Fibre Channel method would fail due to transmission errors within the first three comma occurrences, extending the time required for symbol lock far beyond the original expectation.
Conventional systems are not efficient in detecting unique bit sequences and maintaining proper alignment. Therefore, there is a need for a method and system that can detect a unique bit stream pattern, monitor a data stream for errors and maintain proper alignment.